A Review on Meta-Heuristic and Reinforcement Learning for VLSI Floor Planning

Abstract

Floor planning is a foundational step in the physical design of very-large-scale integration (VLSI) circuits, directly influencing chip area utilization, interconnect length, and overall performance. Owing to the NP-hard nature of both two-dimensional (2D) and three-dimensional (3D) floor planning problems, exact optimization methods become computationally prohibitive as design complexity increases. This paper provides a comprehensive survey of two major solution paradigms: classical meta-heuristic algorithms and modern reinforcement learning techniques. We first review widely adopted meta-heuristics-including simulated annealing, genetic algorithms, particle swarm optimization, and ant colony optimization-highlighting their operational principles, strengths in global search, and practical challenges related to parameter tuning and convergence. Next, we explore reinforcement learning frameworks that cast floor planning as a sequential decision-making task, with deep reinforcement learning agents capable of learning placement policies in high-dimensional spaces. Comparative analysis reveals that while meta-heuristics excel in adaptability and ease of implementation, reinforcement learning offers potential for automated, data-driven optimization with reduced manual intervention. Finally, we discuss emerging hybrid approaches that integrate meta-heuristic exploration with learned policy refinement, pointing toward future research directions aimed at achieving efficient, high-quality layouts for next-generation VLSI designs.