Design and Implementation of SHA-512 Hash Function IP Core
DOI:
https://doi.org/10.6919/ICJE.202511_11(11).0013Keywords:
Hash Function; SHA-512; FPGA; IP Core; Message Padding; Message Compression.Abstract
To meet the requirements of verifying the correctness, integrity and whether the configuration file has been tampered with during the remote upgrade process of the FPGA configuration file, a SHA-512 IP core is designed to implement the digital signature verification of the configuration file on the FPGA. To facilitate interaction with other modules, the IP core adopts the AXI-stream interface to receive message data. A pipeline design approach is used to make message padding, message expansion and message compression proceed in sequence, reducing the processing delay of the IP core. No third-party IP cores are used in the design, making it easy to transplant and deploy on other domestic FPGAs. Finally, the designed IP core is tested on the AMD XC7K325TFFG676 chip. The test results show that the IP core can perform hash operations on messages and has stable performance.
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Copyright (c) 2025 International Core Journal of Engineering
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